Power Efficient MAC Unit Based Digital PID Controllers

Proper closed loop has been an ever hot issue in the automotive industry. The industrial equipments governed by PID controllers have very simple control architecture and efficiency but still they find a trouble dueto large power consumption and slow mathematical computation. Many researchers have worked out and are trying to design a low power, less delay PID. This paper reviews three MAC architectures with array, booth and wallace tree multipliers incorporated in PID architecture. The simulations are done and the area, power, delay results are synthesized using Xilinx ISE. Comparisons are made between these three architectures in terms of power delay product and area delay product


INTRODUCTION
With the fast growth in the development of industrial equipments, engineers are in search of efficient control structures. Proportional-Integral-Derivative (PID) controller strongly captures its place in industries such as robotics, automation systems, aerospace and process control because of its very simple control structure, remarkable efficiency, robust performance and low power consumption. A PID will make the output plant to operate in the desired manner, causing the output to follow a reference input signal. For the proper tracking of output in relation to its reference, controllers are in need of less delay (i.e., quick computation of inner arithmetic operations) architectures. The various modules in controllers are designed with the help of state machines [1]. The looping of multipliers from controllers are shown in [2]. Seven adders based PID controllers and a vedic multiplier based controller are simulated and the results are compared for the efficient one [3]-[4]. The MAC flow diagram for various digital applications are shown [5]. This paper presents significant Multiplier-Accumulator (MAC) architectures with three different multipliers of PID which highlights on high speed, low power consumption. The comparisons are done among the multiplier, MAC unit and the PID architectures.

Fig.1. PID general architecture
The controller's output is the summation of proportional, integral and derivative gains which is given by, The output equation is abbreviated with the error signal as I S S N 2321-807X V o l u m e 1 2 N u m b e r 9 J o u r n a l o f A d v a n c e s i n C h e m i s t r y 4325 | P a g e S e p t e m b e r 2 0 1 6 w w w . c i r w o r l d . c o m Where, Kp is the proportional gain, Ti is the integral time constant and Td is the derivative time constant. The block diagram of PID is depicted in Fig. 1.
Where, R, e and u represents the reference input, error signal and output of the controller. There are many tuning schemes are proposed for the efficient operation of PID controller. This paper gives special attention to the inner architecture especially on multiplier which decides the entire controller performance.

1.Multiply-Accumulator Block
The error signal which is calculated by subtracting the reference signal and the output is given as input to the multiplier. The adder receives input from the multiplier and the previously accumulated value from the shift register as shown in Fig.2. The choice of the multiplier depends on the application. Array multipliers usually have regular structures and are easy to expand. The partial products are generated by multiplying the multiplicand with their respective multiplier bits. The generated partial products are shifted according to their bit orders and then added as in Fig.3. Array multiplication needs to add as many partial products as there are in multiplier bits. The generation of A partial products requires A×B two-bit AND gates.
The multiplier utilizes more area for addition of N partial products which require (N-1)M bit adders. The array structure makes it difficult to measure the propagation delay.

Fig.2. 4-bit array multiplier
A booth multiplier consists of a booth encoder, carry save adder tree to add partial products and a final adder for the result. This approach utilizes fewer additions and subtractions than that of straight forward algorithms. The partial products generated using booth encoder is given as input to the carry save adder so that sum and carry outputs are obtained. The number of partial products generated in booth algorithm is halved when compared to array multiplier. A wallace tree multiplier uses three steps for multiplying two numbers such as the bit products are formed, the bit product matrix is reduced to a two row matrix where sum of the row equals the sum of bit products, and the two resulting rows are summed with a fast adder to produce a final product. It is a tree multiplier with carry save adders as in Fig.3 which in turn consists of the most common ripple carry adders and full adders. The circuit layout is not easy but operating speed is high. The output from the multipliers is added with the previously accumulated value. The adder used here is the Ripple carry adder.  A ripple carry adder is simply several full adders connected in series such that the carry can propagate through full adder before the addition. The carry propagation chain will determine the latency of the entire ripple carry adder circuit. A register is a group of binary storage cells (such as flip flops) capable of holding binary information. It also has the combinational part for data processing tasks. There are a group of flip-flops connected in a chain so that the output from one becomes the input of the next which. All the flip flops are driven by a common clock, and all are set or reset simultaneously. When there is a clock signal, the inputs D0,D1….D7 are loaded parallel into the register and the outputs Q0,Q1,….Q7 are also available in parallel at the output. All the data gets shifted simultaneously during a single clock cycle. Parallel shifting is much faster than serial shifting.

2.PID with Proposed MAC Unit
PID Controller is used in higher order dynamics. The two standard versions of PID are the incremental form and the commercial form. Both architectures are well suited for PID redundant architecture depending upon the application. In commercial form the transfer functions are approximated by limiting the derivative gain and setpoint weight. The designed MAC unit is embedded in the PID architecture. Due to quick computation of arithmetic operations, the controller is able to calculate its error value for next cycle. The designed PID can be used for various closed loop performance. Uc(k) is the reference signal and Y(k) is the feedback stored in the register. The error signal is measured by calculating difference between the reference value and the previous value stored in the register. When there are four inputs, DMAC (Double MAC) instead of MAC is used to reduce the complexity.The coefficients of PID are utilized in the architecture as per the equations. The subtractor subtracts the two values and stored in a register for future operations as in Fig. 4. The commercial PID overcomes the drawbacks of incremental PID and can be used for all individual and combinations of controllers.
I S S N 2321-807X V o l u m e 1 2 N u m b e r 9 J o u r n a l o f A d v a n c e s i n C h e m i s t r y 4327 | P a g e S e p t e m b e r 2 0 1 6 w w w . c i r w o r l d . c o m

Results and Discussions
The VHDL coding for array, booth and wallace tree multiplier is written and their functions are verified using Modelsim 6.2c. The power results for these multipliers are synthesized using Xilinx ISE 13.2 and are tabulated. The multiplier block output is given to a adder and an accumulator so that it constitutes a MAC unit for PID structure. The booth multiplier shows a better power result of 0.41mW when compared to array and wallace tree multipliers whics shows 0.86mW and 0.64mW respectively. Likewise the power analysis has been done for three MAC units and their comparisons done in the following tables. The power result shows that the MAC unit with booth multiplier has better performance than the other two multipliers. Using these MAC unit, the PID architecture are simulated in the System Generator.   The booth multiplier based PID consumes less power and shows good power delay product. Wallace tree based PID depicts better result in terms of area. The booth based commercial PID also simulated as it consumes low power. Wallace tree based PID 320 The commercial architecture consumes same power as incremental but delay is slightly higher of 10ns because the structure is quite complicating.

Conclusion
Different multiplier based MAC unit has been designed and the power results are compared for better performance of PID controller. The booth based PID architecture consumes less power when compared to array based PID and wallace tree based PID architectures. The wallace tree PID architecture utilizes less area and delay than the other two. The power delay product(PDP) is better for booth architecture. So that the booth architectures will find its application in power constrain industries and wallace tree architectures will suit for area constrain industries.