A Review Paper on Comparative Study of FPGA Implementation of Adhoc Security Algorithms

Nowadays data security is an important issue for decentralized networks like Adhoc Network. In this paper, we have proposed the study of five FPGA implementated data security algorithms specially designed for adhoc network. We have proposed the role of FPGAs within a security system and provided the solutions to security challenges. The result shows that FPGA implementation outperforms software and processors implementation by 20 and 140 times respectively


INTRODUCTION
In todays scenario, telecommunication technologies are advanced to provide networking facilities even in remote areas where predesign network infrastructure is not available. A decentralized node network where a number of nodes can communicate with each other anytime and anywhere called Adhoc network, which is applicable in such fields. Mobile ad hoc networks (MANETs) are a collection of wireless hosts that communicate with each other through multi-hop wireless links, without the existence of any infrastructure or administrative authority. Therefore nodes must collaborate between them to accomplish some operations like routing and security. Adhoc networks have wide applications in professional, military, and rescue operation fields where it is required to share data efficiently and fastly without any infrastructure assistance [1]- [5].
As we have seen above that Adhoc network is being used for defence and rescue operation fields, where the information being transmitted is highly confidential. Security of such information, is important and hence security is a main issue for adhoc networking. Wireless networks are more prone to security attacks as all transmissions are carried out using the air medium. They are especially susceptible to attacks of eavesdropping, replay and spoofing. These systems therefore need to have built-in features to withstand these attacks without compromising security in any way. The classification of security services in any network can be given as follows: Confidentiality, Encryption, Integrity, Access Control and Availability. While designing an adhoc network, security algorithms also need to be implemented to maintain the secracy of the data. Two kinds of security algorithms are designed for adhoc networks namely symmetric algorithms (conventional encryption) and asymmetric algorithms (public key encryption) [6]- [8].
For implementing the security algorithms upon practical system, three main approaches are followed eg: microprocessors, ASIC and FPGA implementations. In this paper, we are emphasizing upon FPGA technology. Security algorithm programs can be return in VHDL or Verilog environment and are downloaded to the FPGA chip. Most of this chip are in circuit programmable and hence the encryption key can be changed online. A gate array is a particular arrangement of transistors fabricated upon a single chip. Different arrangements of inter-connect metal layers can be added in order to define the function of the circuit. This allows that same mass produce wafers can be used for performing different logic functions. Field programmability is the property that allows the functionality of a device to be modified according to the program. FPGA circuits utilizing SRAM and EPROM programming technologies are volatile in nature that is same circuit can be modified according to different digital function. Device configuration can be programmed to be portable between miscellaneous FPGAs without any adaptation. FPGAs also provide extremely short time to market due to earlier availability of hardware prototypes. FPGA system works very efficiently as it is exactly customized for the designated task. High performance gain can be achieved by providing parallelization and customization for the specific task. FPGA technology provides real time deterministic behavior of the system. On the basis of these facts now it is clear that fabrication technology is being shifted from ASIC to FPGA [9]- [11].

Clustering algorithm
Software implementation of clustering algorithms have been suffered from power limitations at the time of high traffic. This algorithm provides solution of that problem by hardware implementation of K-means algorithm which is based on cluster based traffic. The advance algorithms for clustering are k-means [12], Hierarchical Clustering [13], Self-Organizing Maps [14] and Principal Component Analysis [15]. The algorithm can be explained as follows: first it takes input as the number of clusters (k) then cluster centers will be created by the random data points. Second arithmetic mean of each cluster will be calculated Euclidean or Manhattan distance measure will be used [16].

Implemented results
Hardware implementation of this algorithm has been performed by The Xilinx ISE and VHDL language [16]. The clock frequency 40 MHZ has been used and 32 packets in 11.8 microseconds has been processed. The result shows that hardware implemented design is 300 times faster than software implemented design.

Scalable encryption algorithm
SEA is a scalable encryption algorithm is the best known hardware algorithm for embedded applications. Initially this was designed for soft ware implementations. SEA has proposed parametric block cipher for resource constrained systems. It has provided low cost and small size encryption/authentication routine17]- [19]. SEA n,b operates on various text, key and word sizes. It is based on a Feistel structure with a variable number of rounds, and is defined with respect to the following parameters: • n: plaintext size, key size.
• n b = n 2b : number of words per Feistel branch. • n r : number of block cipher rounds. As only constraint, it is required that n is a multiple of 6b (see [1] for the details). For example, using an 8-bit processor, we can derive a 96-bit block ciphers, denoted as SEA 96,8 . N o v e m b e r , 2 0 1 3 Let x be a n/2 -bit vector. We consider two representations: • Bit representation: x b = x( n/2 − 1) . . . x(2) x(1) x(0). • Word representation: x W = x n b −1 x n b −2 . . . x 2 x 1 x 0 .

Implemented results
In this implementation, the generic VHDL coding has been provided for flexibility. The presented parametric architecture supports both encryption and decryption at a minimal cost. As we know that in VLSI design: less area, maximum efficiency, high speed, time to market and low power consumption are the key issues. In this aspect, SEA exhibits very small area utilization and it is best solution for embedded applications [20].

NTRU-based algorithm
The NTRU (Nth degree truncated polynomial ring) encrypt algorithm provides low power consumption and high efficiency for complex security algorithms. Its public key cryptosystem is based on solution of lattice problems and concept of ring theory. It provides a ring R and two ideals p and q in R. Most of the computations are done on mod p or mod q, and all polynomials are taken modulo (XN_1). NTRU polynomial multiplier is used as star multiplication for multiplication in the ring [21]- [23]. Figure 1 shows the diagram of NTRU polynomial multiplier.

Implemented results
For hardware implementation, figure 2 has proposed the design procedure. The polynomial operands can be represented for chosen to maximize storage efficiency. By the help of minimization of number of gates, number of glitches and size of transistors, this algorithm has been reduced both static and dynamic power dissipation [24].

Galois finite field algorithm
In this algorithm, network decoding scheme based on galois finite field operation has been described. The decoding mechanism needs higher complex mathematical operations as compared to encoding mechanism. Network coding is much more efficient than forward coding because multi cast process is completed in the single phase. Gaussian elimination and high probalitic algorithms is the heart of this prominent scheme. Encoding and decoding finite fields are divided in to prime fields and extension binary fields. For generation of the superior coefficient matrix, echeloning process has been used. Back substitution process has been dedicated for parallelism. The figure 3 has proposed the hardware implementation of decoding process. N o v e m b e r , 2 0 1 3 Implemented results VLSI implementation has been done by the help of VHDL (Very High Speed Hardware Description Language). The results has explained that there is the achievement of twice of the throughput due to the pipelining of echeloning and back substitution process [26].

HCgorilla double cipher algorithm
HCgorilla is the latest algorithm for reduced power dissipation in multimedia data. This hardware algorithm is based on the analysis of internal behaviour of processors. It is capable for bidirectional communication by the help of parallelism. This algorithm includes the following steps: Architecture level parallelism, Circuit module level, Instruction level parallelism and micro architecture level. HCgorilla has proposed for ubiquitous computing due to its functionality and usability. It has composed of 8 Java-compatible instructions with 2 SIMD mode cipher instructions. [27][28][29]. Figure 4 has been proposed the double cipher mechanism. Implemented results VLSI Implementation of above algorithm has composed with two processes: Simulation in Verilog-HDL and Synthesis in VHDL.It has used the 128-word length of the optimum buffer and 0.18-μm standard cell CMOS chip technology. The results have been found that 275 mW power consumption at 200 MHz clock frequency. The evaluation shows that HCgorilla is a high performance and reduced power consumption approach for secure adhoc networks. Figure 5 has proposed the architecture of HCgorilla [30]. N o v e m b e r , 2 0 1 3

CONCLUSION
In this paper, we have surveyed the FPGA implemented security algorithms for Mobile adhoc networks. We gave a brief description about all the recent schemes discussed above and then implemented results have been provided. In this paper, the great importance of VHDL, Verilog and FPGA has been shown. The Analysis gave a interesting result that the HCgorilla is a high-performance hardware approach for secure multimedia data and Secure Cluster Algorithm provides the rebuilding and recovering mechanism so it is able to resist attacks on the cluster structure. The result shows that FPGA implementation outperforms software and processors implementation. Scopes for further research include some challenges like low power dissipation, reliability, energy saving and testing methodologies.